PowerLattice raised $25 million in a Series A round, bringing its total funding to $31 million since its 2023 founding. The round was co-led by Playground Global and Celesta Capital, with notable involvement from former Intel CEO Pat Gelsinger as a board member via Playground Global.
PowerLattice Technologies, a Vancouver, WA-based semiconductor startup, emerged from stealth with its Series A announcement. Founded in 2023 by engineering veterans from Qualcomm, NUVIA, and Intel, the company targets the escalating power demands of AI accelerators. Its core innovation, a compact power delivery chiplet, integrates directly into processor packages, minimizing energy loss and enabling higher performance without major redesigns.
The $25 million round reflects strong validation from deep tech VCs. Playground Global, known for backing transformative hardware like those at xAI and Groq, co-led alongside Celesta Capital, a firm focused on semiconductor supply chain advancements. Pat Gelsinger’s participation underscores the technology’s potential, drawing on his Intel tenure where power efficiency was a perennial challenge.
At its heart, PowerLattice’s chiplet uses miniaturized on die inductors and advanced voltage controls to deliver power precisely where compute happens, slashing losses that traditionally occur in external supplies. Early silicon prototypes are already in production at TSMC, with engineering samples targeting high wattage GPUs and CPUs. This could effectively double AI workload efficiency, easing data center cooling and electricity costs amid projections of AI power needs rivaling small countries.
With samples shipping to potential partners like NVIDIA and AMD in 2026, PowerLattice aims for rapid adoption. The company plans a larger follow on round to scale manufacturing, positioning itself in a market where energy constraints could bottleneck AI growth. While promising, success hinges on seamless integration and proving reliability at scale.
PowerLattice Technologies’ latest funding round marks a pivotal moment for a startup tackling one of the most pressing bottlenecks in artificial intelligence: power efficiency. The $25 million Series A infusion not only validates the company’s technical approach but also signals broader industry urgency around sustainable compute scaling.
The Series A round, valued at $25 million, was co-led by Playground Global and Celesta Capital, elevating PowerLattice’s cumulative funding to $31 million. This implies an earlier seed round of approximately $6 million, likely used for initial R&D and team assembly post 2023 founding. While specific valuation details remain undisclosed, a common practice in early stage hardware deals, the round’s structure emphasizes strategic rather than purely financial milestones. Funds are earmarked for accelerating chiplet production, expanding engineering samples, and forging partnerships with major chipmakers. No debt components or secondary sales were mentioned, keeping the focus on growth equity.
| Funding Stage | Amount Raised | Date | Lead Investors | Total Funding to Date |
| Seed | ~$6M | 2023-2024 | Undisclosed | $6M |
| Series A | $25M | Nov 17, 2025 | Playground Global, Celesta Capital | $31M |
This table illustrates the rapid escalation typical of AI adjacent hardware startups, where proof of concept silicon (already achieved here) de-risks subsequent raises.
PowerLattice was co-founded by Dr. Peng Zou (CEO and President), Gang Ren, and Sujith Dermal, a trio with over 50 combined years in power management and analog IC design. Zou, previously at Qualcomm and NUVIA (acquired by Qualcomm in 2021), led the vision for on package power integration. Ren and Dermal bring Intel honed expertise in system design and magnetics, backed by a portfolio of patents in miniaturized inductors. Headquartered in Vancouver, WA (with ~20 employees), and an engineering hub in Chandler, AZ, the company operates in the Pacific Northwest’s burgeoning semiconductor corridor, near Intel’s Hillsboro fabs.
The team’s “dream team” composition, as dubbed by investor Pat Gelsinger, stems from their direct experience with power related failures in prior roles, such as thermal throttling in high performance chips. This insider perspective positions PowerLattice not as a speculative entrant but as a targeted solution provider.
Technological Innovation: Breaking the AI Power Wall
PowerLattice’s flagship product is the industry’s first dedicated power delivery chiplet, a modular silicon component that embeds power conversion directly within the processor package. Traditional architectures route power externally, incurring 20-30% losses via long traces and voltage droops. PowerLattice’s design counters this with:
- Proprietary on-die magnetic inductors: Miniaturized to fit alongside compute dies, enabling vertical stacking.
- Advanced voltage regulation: Programmable circuits for real time precision, reducing throttling.
- Software layer: For dynamic tuning, optimizing across workloads.
The result? Over 50% reduction in total system power for AI accelerators, effectively doubling compute density without increased energy draw. For context, a 1KW+ GPU could see its power budget halved, translating to fewer data center racks and lower cooling needs, critical as AI training clusters now consume gigawatts, rivaling nuclear plants.
Silicon validation is advanced: TSMC has taped out initial runs, with engineering samples en route to undisclosed partners for 2026 trials. Integration is “drop in” compatible with existing SoCs from NVIDIA, AMD, and Broadcom, minimizing adoption barriers. Reliability metrics emphasize AI grade stability, with sub millisecond response times to prevent crashes under bursty inference loads.
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Investor Perspectives and Strategic Fit
Playground Global’s lead, helmed by Gelsinger, reflects a bet on “generational leaps” in computing infrastructure. Gelsinger, who navigated Intel’s power crises during his CEO stint, noted: “AI is not constrained by capital, it’s constrained by power.” Celesta Capital’s Dr. Steve Fu echoed this, praising the solution’s scalability for data center bottlenecks like cost, reliability, and cooling. Fu’s background in power device incubation at global semis adds credibility, as he highlighted two decades of failed attempts by incumbents.
This round aligns with VC trends: Deep tech funds poured $50B+ into semiconductors in 2024-2025, per PitchBook data, with power efficiency sub themes surging amid U.S. CHIPS Act incentives. PowerLattice’s PNW base taps regional grants, potentially amplifying the raise’s impact.
The “AI power wall” looms large: Gartner forecasts data center power demand doubling to 1,000TWh by 2026, straining grids and inflating costs (e.g., $0.10/kWh in hyperscalers). NVIDIA’s Blackwell GPUs already push 1,000W+ per chip, exacerbating this. PowerLattice enters a niche where software optimizations alone fall short, complementing efforts like ARM’s low power cores.
Key competitors include:
- Empower Semiconductor: A direct rival with integrated voltage regulators; raised $140M Series D in September 2025, focusing on similar on package delivery but with broader IoT applicability.
- Incumbents like Infineon and Texas Instruments: Offer discrete power ICs but lack chiplet modularity.
- Emerging players: d-Matrix and NextSilicon (Playground backed) integrate power in custom AI chips, potentially overlapping.
PowerLattice differentiates via its AI specific focus and >50% efficiency gains, but faces risks in ecosystem lock in (e.g., NVIDIA’s CUDA moat). Market share projections are optimistic: If adopted in 10% of next gen accelerators, it could capture $500M+ annually by 2028, per analogous chiplet ramps like AMD’s.
While technically sound, hurdles remain: Proving multi die compatibility at exascale, navigating supply chain volatility (TSMC’s queue), and scaling software ecosystems. Geopolitical tensions could disrupt AZ operations near Taiwan dependent fabs. Positively, this round could catalyze a power renaissance, enabling greener AI, reducing CO2 from training models equivalent to 5 million cars annually.
Social media echoes enthusiasm, with early posts amplifying the Gelsinger angle and efficiency claims, though volume is nascent given the announcement’s recency.
Prospective Roadmap and Ecosystem Integration
PowerLattice eyes 2026 as a breakout year: Widespread sampling with hyperscalers, followed by volume production. A “much larger” Series B is anticipated to fund fabs and sales teams. Long term, it could spawn standards for power chiplet interfaces, akin to UCIe for interconnects. Partnerships with NVIDIA/AMD trials suggest co-design wins, potentially embedding the tech in Hopper/Blackwell successors.
In sum, this funding cements PowerLattice as a linchpin in AI’s sustainable evolution, blending proven talent with timely innovation. As Gelsinger quipped, it’s not just about chips, it’s reshaping computing’s energy frontier.
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